This paper presents an FPGA tech-mapping algorithm dedicated to security applications. The objective is to implementââ?¬â?on\r\na full-custom asynchronous FPGAââ?¬â?secured functions that need to be robust against side-channel attacks (SCAs). The paper\r\nbriefly describes the architecture of this FPGA that has been designed and prototyped in CMOS 65nm to target various styles\r\nof asynchronous logic including 2-phase and 4-phase communication protocols and 1-of-n data encoding. This programmable\r\narchitecture is designed to be electrically balanced in order to fit the security requirements. It allows fair comparisons between\r\ndifferent styles of asynchronous implementations. In order to illustrate the FPGA flexibility and security, a case study has been\r\nimplemented in 2-phase and 4-phase Quasi-Delay-Insensitive (QDI) logic.
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